The WY5709-T2 provides a dual-port fully integrated Layer 4 and Layer 5 solution - TCP/IP RDMA and iSCSI along with two complete 10/100/1000BASE-T Gigabit Ethernet Physical Layer Devices IEEE 802.3 compliant Media Access Controls (MAC) and Physical Layer Transceiver solution for high performance network applications. By itself the Chipset BCM5709C provides a complete dual-port single-chip Gigabit Ethernet NIC with TCP/IP Processing Engine Full Fast-path TCP processing engine supporting IPv4 and IPv6RDMA NIC (RNIC) iSCSI HBA or LOM solution.
Standard Compliant PCI express base SPEC 2.0 and backward compatible with SEPC 1.1 & 1.0a PCI Power management SPEC 1.2 Supports 10/100/1000Mbps data rate auto negotiation operation Supports PCI Express 1.1 Supports pair swap/polarity/skew correction Crossover Detection & Auto-Correction Wake-on-LAN and remote wake-up support
Performance Features: 16 Transmit and Receive queues per port Up to 16 queues of Receive Side Scaling (RSS) minimize CPU utilization across multiple processor systems; Support for 8 pools of virtual machine Device Queues ( VMDq) per port Support Direct Cache Access ( DCA) Support Intel I/O AT 2.0 TSO interleaving for reduced latency UDP TSO Minimized device I/O interrupts using MSI and MSI-X Offload of TCP / IP / UDP checksum calculation and TCP segmentation SCTP receive and transmit checksum offload Packet interrupt coalescing timers (packet timers) and absolute- delay interrupt timers for both transmit and receive operation Copper Gigabit Ethernet 1000Base-T: Independently copper Gigabit Ethernet channels support Single Gigabit Ethernet (1000Base-T) Fast Ethernet (100Base-Tx) and Ethernet (10Base-T) Triple speed 1000Mbps (1000Base-T) 100 Mbps (100Base-Tx) and 10 Mbps (100Base-T) operation N-way auto negotiation automatic sensing and switching between 1Gbps full duplex and 100 / 10 Mbps operations Simplex or Full Duplex RJ-45 female connectors Common Key Features: Host Interface standard support PCI-Express Base Specification Revision 1.1. High performance reliability and low power use in Intel 82576 Dual integrated MAC + PHY and SERDES chip Controllers Ultra deep packet buffer per channel lowers CPU utilization Hardware acceleration that can offload tasks from the host processor. The controllers can offload TCP/UDP/IP checksum calculations and TCP segmentation Server class reliability availability and performance features: Link Aggregation and Load Balancing: Switch dependent: 802.3ad (LACP) Generic Trunking ( GEC / FEC) Switch and NIC Independent Failover Priority queuing – 802.1p layer 2 priority encoding Virtual LANs –802.1q VLAN tagging Jumbo Frame (9.5KB) 802.x flow control PCI-SIG SR IOV (8 VF) Multi-cast/ broadcast Packet replication Statistics for SNMP MIB II Ethernet like MIB and Ethernet MIB (802.3z Clause 30) Supports Vital Product Data (VPD) Integrated LinkSec security engines Supports IEEE 1588 LEDs indicators for link/Activity/Speed status Copper Gigabit Ethernet Technical Specifications - (1000Base-T) Adapters: IEEE Standard / Network topology: Gigabit Ethernet 1000Base-T